In a communication network including a number of transmission apparatuses, data providing various services (e.g., audio, moving picture, and user data) are transmitted.
Such transmission apparatus may collect statistics information in the form of the number of data pieces passing through the apparatus itself or the size of each data pieces for each service with the intention of monitoring a state of traffic of each service.
As one example, a hardware counter equipped with a counter processor and a memory is implemented in an interfacing section of a transmission apparatus. With this configuration, the counter processor counts the statistics information and stores the result of the counting into the memory.
The statistics information stored in the memory is collected and compiled by, for example, a controller that controls the transmission apparatus and may be displayed on a user interface (e.g., on a display screen) of the transmission apparatus.
The Patent Literature 1 discloses an accumulation processor equipped with an adder and a counter that counts the number of times of occurring a carry signal in the adder, so that the load on the accumulation processor can be reduced.
Patent Literature 1: Japanese Patent Publication No. SHO 59-121541
In the above method, overflow of the memory is avoided by the controller initializing (clearing) the value of the memory after reading the statistics information from the memory, for example. Here, the phenomenon “overflow” is caused when a count value to be input into the counter is larger than the capacity of the counter (i.e., the upper limit of the countable value of the counter determined in terms of the memory capacity (i.e., the bit width) of the counter).
However, if the memory overflows before the controller clears the value of the memory, the controller cannot collect and compile the statistics information correctly.
One of the solutions to the problem is to implement a memory that has a sufficiently large capacity (bit width) in the transmitting apparatus so that the memory would not overflow despite a large amount of traffic through the transmission apparatus before the controller collects the statistics information.
In accordance with recent increase in speed of a transmission apparatus and in density of the number of services accommodated, the number of data pieces passing through the transmission apparatus and the sizes of such data pieces are expanding. This leads a significant increase in amount of statistics information collected and compiled by the controller.
Here, the capacity of the memory can be expressed by the following formula (1).Memory_Size(bit)=Bit_width(bit)×entry_num(pcs)  (1)
where, “Memory_Size” represents the capacity of the memory; “Bit_width” represents a bit width of an extent that does not cause overflow; “entry_num” represents the number of entries whose statistics information is to be monitored.
For example, when the transmission apparatus monitors statistics information for each user, the “entry_num” is identical to the maximum number of users being in charge of the transmission apparatus.
The numbers of “Memory_Size”, “Bit_width”, and “entry_num” are natural numbers. Here the unit [pcs] of the “entry_num” is an abbreviation of piece.
The “Bit_width” is calculated by the following formula (2).Bit_width(bit)>log2[Max(V—PS)×Polling_cycle]  (2)
where, “Max (V_PS)” represents a maximum amount of data passing through the transmission apparatus per second; “Polling_cycle” represents an interval between collections of the statistics information by the controller. Here, when the hardware counter counts the number of frames passing through the transmission apparatus, Max(V_PS) represents the maximum number of frames per second while when the hardware counter counts the number of bytes of data, Max(V_PS) represents the maximum number of bytes per second. The value of the Max(V_PS) is determined in terms of, for example, the physical speed of the interface section of the transmission apparatus and the kind of object to be counted.
Here, assuming cases where an interface (e.g., a data communication card) having an interfacing speed of 100 Gbps monitors services for each users (the number of users is 65536 [pcs]). For example, when the number of bits of data is to be monitored, Max (V_PS) is 100×108, and, even if the “Polling_cycle” is set to be 1 second, the “Bit_width” is as much as 34 bits from the formula (2).
The “entry_num” being 65536 [pcs] determines the memory capacity “Memory_Size”=2,228,224 bits≈2.2 M bytes on the basis of the formula (1).
Normally, since each service supports several to several dozens kinds of statistics information piece, the memory requires a capacity as large as several dozens mega bits.
As a consequence, the number of memories implemented in the hardware counter to collect and compile such statistics information pieces increases, which may hinder the integration of the hardware from aspects of the implementation area and consumption power.
In addition, even when the number of users is small, a memory dedicated to counting statistics information is required if an internal memory of the Application Specific Integrated Circuit (ASIC) or the Field Programmable Gate Array (FPGA) is insufficient or cannot be used without restriction, which may also hinder the integration of the hardware.